A VHDL Component Model for Mixed Abstraction Level Simulation and Behavioral Synthesis*

In the high-level synthesis domain, the integration of user defined RT components in the algorithmic specification plays an important role. The implementation of VHDL models emulating specific functional and timing behavior at the algorithmic level is expensive and time-consuming. Moreover, particular functional and timing behavior can only be implemented at the RT level, e.g. interrupt handling, and interface components. Therefore, this paper presents a new approach for designing VHDL models for mixed abstraction level simulation and behavioral synthesis. The VHDL standard without any extensions is used. Procedures implement the communication between algorithmic descriptions and VHDL components at the same or at lower levels of abstraction. A VHDL preprocessor reduces the design time necessary for the specification of this communication. The different timing aspects of the algorithmic and the RT levels are encapsulated in the used procedures. Last of all, an appropriate stimuli set can easily be included.